features compatible with cs5012, cs5012a, cs5014, cs5016 pc/ m p-compatible header connection 16-bit parallel data end-of-conversion output cs, rd, and a0 control inputs dip-switch selectable: unipolar/bipolar input range burst & interleave calibration modes continuous conversion adjustable voltage reference serial data and clock bnc connections operation from internally-generated or externally-supplied master clock general description the CDB5012/4/6 is an evaluation board that eases the laboratory characterization of any of the cs5012, cs5012a, cs5014 and cs5016 a/d converters. the board can be easily reconfigured to simulate any com- bination of sampling, master clock, calibration, and input range conditions. the converters parallel output data are available at a 40 pin strip header allowing easy interfacing to pcs or microprocessor busses. output data is also available in serial form at sclk and sdata coaxial bnc connec- tors. evaluation can also be performed over a wide range of input spans using the on-board reference circuitry. fur- thermore, the CDB5012, CDB5012a, cdb5014, cdb5016 features dip-switch selectable unipolar/bipo- lar input ranges and the interleave calibration mode. calibration can be initiated at any time by momentarily depressing a reset pushbutton. ordering information: CDB5012, CDB5012a, cdb5014, cdb5016 mar 95 ds14db11 1 cryst al s e mico nd uct o r corp orat ion p . o. box 17847, aus t in, tx 78760 ( 512) 445 7222 fax : ( 512) 445 7581 evaluation board for cs5012, cs5012a, cs5014, cs5016 adcs semiconductor corporation CDB5012 CDB5012a cdb5014 cdb5016 d0 - d15 a0 rd eoc cs h e a d e r sclk sdata reset ain clkin hold gnd -5v +5v voltage reference a/d converter cs5012a cs5014 cs5016 cs5012 copyri ght ? cryst al s e m i conduct o r corporati on 1995 (a l l ri ghts reserved)
analog input the analog input to the a/d converter is supplied through the bnc coaxial connector labeled ain. analog input polarity is controlled by the first position switch on the dip-switch, sw-1. if it is on, the input is unipolar ranging from gnd to vref. if the switch is off, the input range is bi- polar with the magnitude of the reference voltage defining both zero- and full-scale ( vref). the a/d converters internal analog input buffer requires a source impedance of less than 400 w at 1mhz for stability. acquisition and throughput are specified assuming a dc source impedance of less than 200 w . infinitely large dc source imped- ances can be accommodated by adding capaci- tance (typically 1000pf) from the analog input to ground. however, high dc source resistances de- grade acquisition time and consequently through- put. cs eoc d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 38 21 22 23 vd- vd+ + 36 11 10 c1 c2 c3 c4 va- va+ 2527 30 c5 c6 c10 c11 + sclk sdata ain clkin 39 40 26 20 32 vref 28 reset 31 tst 29 refbuf r10 c7 r8 r9 sw2 vd+ u1 reset vd+ r23 (optional) va- d0 c12 sw1-4 + + 37 eot hold 1 r3 +5v -5v vd+ vd- r1 r2 va+ va- rd r7 r5 vd+ r4 24 34 35 bp/up cal intlv sw1-1 sw1-2 sw1-3 33 bw r12 r 13 r11 r 6 cs5012a cs5014 cs5016 cs5012 figure 1. CDB5012, CDB5012a, cdb5014, cdb5016 schematic (reference circuitry appears in figure 3) CDB5012, CDB5012a, cdb5014, cdb5016 d s 14db1 1 2
initiating conversions a negative transition on the converters hold pin places the devices analog input into the hold mode and initiates a conversion cycle. on the CDB5012, CDB5012a, cdb5014, cdb5016, this input can be generated by one of two means. first, it can be supplied through the bnc coaxial connector appropriately labeled hold. alterna- tively, switch position 4 of the dip-switch can be placed in the on position, thus looping the con- verters eot output back to hold. this results in continuous conversions at a fraction of the master clock frequency (see "synchronous opera- tion" in the converters data sheet). the a/d converters eot output is an indicator of its acquisition status; it falls when the analog input has been acquired to the specified accuracy. if an external sampling clock is applied to the hold bnc connector, care must similarly be taken to obey the converters acquisition and maximum sampling rate requirements. a more detailed discussion of acquisition and throughput can be found in the converters data sheet. the CDB5012, CDB5012a, cdb5014, cdb5016 is shipped from the factory without the hold bnc input terminated for operation with an external sampling clock. however, location r23 is reserved for the insertion of a 51 w resis- tor to eliminate reflections of the incoming clock signal. voltage reference circuitry the CDB5012, CDB5012a, cdb5014, cdb5016 features an adjustable voltage refer- ence which allows characterization over a wide range of reference voltages. the circuitry consists of a 2.5v voltage reference (1403) and an adjust- able gain block with a discrete output stage (figure 3). the output stage minimizes the outputs head- room requirements allowing the reference voltage to come within 300mv of the positive supply. the coarse and fine trim potentiometers are fac- tory calibrated to a reference voltage of 4.5v (a table of output code values for a reference volt- age of 4.5v appears in the cs5012, cs5012a, cs5014, cs5016 data sheets). when calibrating the reference, the voltage should be measured di- rectly at the vref input (pin 28) or at the un- grounded lead of decoupling capacitor c9. on unipolar normal operation interleaved cal continuous conversion off bipolar burst cal * normal normal position 1 position 2 position 3 position 4 * note: use of burst cal is not recommended. figure 2. dip-switch definitions + - r14 c13 r15 q1 r17 r16 c14 r18 u3 c8 vref va+ coarse adjust c9 u2 + op-07 1403 r21 r22 r19 r20 trim fine figure 3. voltage reference circuitry CDB5012, CDB5012a, cdb5014, cdb5016 3 d s 14db11
reset/self-calibration modes the a/d converter will usually reset itself upon power-up. since this function is not guaranteed, the converter must be reset upon power-up in system operation. the converter can be reset on the CDB5012, CDB5012a, cdb5014, cdb5016 board by momentarily depressing push-button sw-2 thus initiating a full calibration cycle; 1,443,840 master clock cycles later the converter is ready for normal operation. the converters also feature two other calibration modes: burst and interleave. the use of burst calibration is not recommended. interleave can be initiated by setting switch position 3 to the on position. in the interleave mode ( intrlv low), the converter appends one small portion of a cali- bration cycle (20 master clock cycles) to each conversion cycle. thus, a full calibration cycle completes every 72,192 conversion cycles. the interleave calibration mode should not be used intermittently. a more detailed discussion of the converters calibration modes and capabilities can be found in their data sheets. parallel output data/microprocessor interface the converters outputs d0-d15, its cs, rd, and a0 inputs, and its eoc output are available at the 40 pin header. the cs and rd inputs are pulled low through 10 k w resistors placing the converter in a microprocessor-independent mode. control input a0 is pulled up, insuring the converters output word, rather than the status register, appears at the header. the converters 3-state output buffers and micro- processor interface can be exercised by driving the cs and/or rd inputs at the header. similarly, the converters 8-bit status register can be ob- tained on d0-d7 by driving a0 low. the converters eoc and data outputs are not buffered on the CDB5012, CDB5012a, cdb5014, cdb5016. therefore, careful attention should be paid to the load presented by any ca- bling, especially if the 3-state output buffers are to be exercised at speed. twisted ribbon cable is typically specified at 10pf/ft, so several feet can generally be accommodated. serial output data serial output data is available at the two bnc connections sclk and sdata. data appears msb first, lsb last, and is valid on the rising edge of sclk. master clock the a/d converter operates from a master clock which can either be internally-generated or exter- nally-supplied. for operation with an external clock, the bnc connector labeled clkin should be driven with a ttl clock signal. the CDB5012, CDB5012a, cdb5014, cdb5016 is shipped from the factory with the clkin input d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 a0 rd d10 d11 d12 d13 d14 d15 eoc cs dgnd dgnd figure 4. header pin definitions CDB5012, CDB5012a, cdb5014, cdb5016 d s 14db1 4
terminated by a 51 w resistor to eliminate line reflections of the incoming clock. if the clkin bnc input is left floating, this resistor pulls the converters clock input down to ground, thus ac- tivating its internal oscillator. decoupling the CDB5012, CDB5012a, cdb5014, cdb5016s decoupling scheme was designed to insure accurate evaluation of the converters per- formance independent of the quality of the power supplies. each supply is decoupled at the con- verter with a 10 m f electrolytic capacitor to filter low frequency noise and a 0.1 m f ceramic capaci- tor to handle higher frequencies. the auto-zero- ing action of the converters comparator provides extremely good power supply rejection at low frequencies. depending on the quality of the sys- tems power supplies, the decoupling scheme could be relaxed in actual use. component list 10 w resistor r1, r2 51 w resistor r3 4.7 w resistor r18 1 k w resistor r9, r14 560 w resistor r17 10 k w resistor r4, r5, r6, r7, r8, r10, r11, r12, r13 2.43 k w resistor r19, r20 3.3 k w resistor r16 240 k w resistor r21 50 k w potentiometer r15 50 k w potentiometer r22 0.068 m f capacitor c14 0.1 m f capacitor c1, c3, c5, c7, c9, c10, c12 10 m f capacitor c2, c4, c6, c8, c11, c13 cs501x/511x a/d converter u1 1403 2.5v reference u2 op07 op amp u3 2n2907a transistor q1 4 pos. spst dip switch sw1 n.o. spst push-button sw2 20 pin header con1 bulkhead bnc con2, con3, con4, con5, con6 red banana jack con7 black banana jack con8 green banana jack con9 1" 4-40 spacer post1, post2, post3, post4, post5, post6 3/8" 4-40 screw sc1, sc2, sc3, sc4, sc5, sc6 CDB5012, CDB5012a, cdb5014, cdb5016 5 d s 14db11
smart analog sdata sclk hold clkin ain gnd +5 -5 r14 coarse c13 r15 u3 u2 q1 c14 r16 r17 r18 r19 r20 r21 r22 fine adj adjustable reference sw2 r8 c12 r9 sw1 on r 10 r1 r2 r11 r12 r13 r 6 cc 34 u1 c5 c6 c7 c8c9 c10 c11 r 7 r 5 r 4 r 3 c1 c2 r23 j1 eoc d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ao rd cs p1 1234 adj evaluation board cdb501x pcb5012-201d top figure 5. board layout CDB5012, CDB5012a, cdb5014, cdb5016 d s 14db1 6
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